1. Field of the Invention
The present invention relates generally to a memory system, and more specifically, to a power management memory system having high performance.
2. Discussion of the Related Art
In order to prevent potentially damaging power consumption, manufacturers and vendors of memory devices, such as dynamic random access memory (DRAM) devices, prescribe specifications for the safe operation of the memory devices. These specifications are often created based on an excessive worst case scenario a memory device may encounter, and not based on the core architecture capabilities of the memory device and real-world conditions.
For example, DRAM vendors may prescribe a particular minimum and maximum time interval for issuing successive xe2x80x9cactivatexe2x80x9d commands of row-address-strobe (RAS) banks within the same DRAM component, such as RAS bank xe2x80x9cAxe2x80x9d, and then a subsequent activate command on RAS bank xe2x80x9cBxe2x80x9d. This time interval is known as xe2x80x9cRAS-to-RAS delayxe2x80x9d, also called xe2x80x9ctRRDxe2x80x9d. However, the maximum tRRD specifications prescribed by the DRAM vendors are typically over-inflated because DRAM vendors assume that an infinite stream of activate commands will be issued to the DRAM device during its operation. Under this assumption, the DRAM vendors define an inflated interval based on this infinite access pattern, which spreads the power dissipation over more time to achieve an average power that is within a safety margin to protect the DRAM device from thermal breakdown.
However, in real-world operation of DRAM devices, infinite streams of activate commands do not occur. Rather, DRAM access utilizing activate commands occurs in xe2x80x9cburstsxe2x80x9d. In other words, typical DRAM access occurs with bursts of activate commands, and the activate commands are not issued in back-to-back infinite streams. Periods of inactivity occur in between these activate command bursts. But, because of the maximum tRRD specifications set forth by the DRAM vendors, which are artificially inflated, the real-world operational nature of DRAM access is not utilized in the most efficient manner possible.